This invention relates to semiconductor packages, and more particularly, to a WBBGA (wire bond ball grid array) semiconductor package, in which a wire bonding distance is shortened.
A BGA (ball grid array) semiconductor package becomes a mainstream product due to its incorporation with sufficient I/O connections in response to high density of electronic elements and electronic circuits. In accordance with increase in the number of the I/O connections, a substrate in the BGA semiconductor package needs to densely accommodate a plurality of bond fingers, for allowing a semiconductor chip to be wire bonded to the bond fingers and then electrically connected to an external circuit.
Generally, a BGA semiconductor package has bond fingers arranged therein in a manner shown in FIG. 1. First, a substrate 10 is prepared for mounting a semiconductor chip 12 thereon, with a plurality of bond pads 122 formed on the chip 12. Then, a plurality of bond fingers 103 are circularly disposed around the chip 12. Finally, a plurality of gold wires 13 are respectively connected to the corresponding bond pads 122 and bond fingers 103, so as to provide an electrically conductive path for the chip 12 to be connected to outside. The structure shown in drawing is exemplified in simplicity, however in practice, the arrangement of bond fingers can be more complicated in a semiconductor package.
However, due to limitation of a conventional etching technology, the bond fingers 103 on the substrate 10 are each dimensioned in width of 3 mils (one mil equals to a thousandth of an inch), and a shortest distance between two adjacent bond fingers 103 is about 3 mils; that is, a 6-mil wide area P is occupied by forming an additional bond finger 103. As shown in FIG. 1, in the provision of the bond fingers 103 circularly surrounding the chip 12, if the chip 12 is considered as a geometrical center of the circle, thus the bond fingers 103 each is spaced from the chip 12 by a shortest distance R of 6n/2xcfx80, wherein n represents the number of the bond fingers 103, and 6n is a circumference of the circle formed by the bond fingers. Similarly, the bond pads 122 on the chip 12 each is spaced from the chip 12 by a shortest distance d, and thus a shortest wire-bonding distance (i.e. wire span, designated by a reference character s) between a bond finger 103 and a bond pad 122 theoretically equals to R-d. As the bond fingers 103 increase in number corresponding to more I/O connections (not shown) incorporated on the substrate 10, the circumference 6n formed by the bond fingers 103 accordingly expand. This therefore unavoidably increases the wire spans s between the bond fingers 103 and the bond pads 122 of the chip 12.
The increased wire span s elongates its wire length, and generally the wire length is about 1.2 times of the wire span. This is disadvantageous for performing a wire bonding process and a molding process, for example, wire sweeping or wire sagging easily occurs to cause short circuit due to impact from a mold flow of a molding compound during molding, as shown in FIG. 2 with dotted lines representing original positions of gold wires 13, which are dislocated due to the mold flow impact indicated by arrows. U.S. Pat. No. 6,031,281 utilizes a plurality of dummy wires to be positioned on a semiconductor chip at where mold flow impact is strongest, so as to enhance resistance of gold wires to the mold flow and reduce the occurrence of wire sweeping. However, the provision of the dummy wires significantly increases complexity and costs in fabrication.
In order to solve the foregoing problems relating to the wire bonding process, U.S. Pat. No. 5,898,213 discloses a method for arranging bond fingers with a shortened wire bonding distance. Compared with the conventional bond finger arrangement, the disclosed method eliminates the drawback of wire length elongating in response to increase in the number of bond fingers. As shown in FIG. 3, this method is characterized in that two sets of bond fingers 110xe2x80x2, 111xe2x80x2 form a circle around a semiconductor chip 12xe2x80x2, and the adjacent bond fingers 110xe2x80x2, 111xe2x80x2 are arranged in a stagger manner, wherein the set of bond fingers positioned more distant from the chip 12xe2x80x2 is referred to as a first set of bond fingers 10xe2x80x2, and the set of bond fingers positioned less distant from the chip 12xe2x80x2 is referred to as a second set of bond fingers 111xe2x80x2. Due to the staggered arrangement of the first bond fingers 110xe2x80x2 and the second bond fingers 111xe2x80x2, thus a shortest distance P2 between the adjacent bond fingers 110xe2x80x2, 111xe2x80x2 is halved to be 3 mils, and a shortest distance (not shown) from the bond fingers to the chip 12xe2x80x2 is reduced to be 3n/2xcfx80(i.e. xc2xdR), which significantly shortens the wire bonding distance.
However, the foregoing method with the shortened wire bonding distance has the following drawbacks. In practical use, the staggered arrangement of the first bond fingers 110xe2x80x2 and the second bond fingers 111xe2x80x2 makes it difficult for accurately bonding gold wires to the corresponding bond fingers, that is, a bonder used for wire bonding can hardly recognize positions of the bond fingers, resulting in the gold wires not bonded to the bond fingers but to conductive traces connected to the bond fingers; this therefore degrades the wire bonding quality.
A primary objective of the present invention is to provide a semiconductor package, in which a plurality of bridging elements are formed between a chip bonding area and bond fingers on a substrate, so as to shorten a wire bonding distance and improve wire bonding operability.
Another objective of the present invention is to provide a semiconductor package, in which resistance to impact of a mold flow is enhanced for gold wires, so as to prevent wire sweeping from occurrence.
A further objective of the present invention is to provide a semiconductor package, in which an existing fabrication technology is employed for disposing a plurality of bridging elements in a stagger manner on a substrate, and this is therefore cost-effective to implement.
In accordance with the above and other objectives, the present invention proposes a semiconductor package, comprising: a substrate having a chip bonding area, and a plurality of bond fingers disposed around the chip bonding area; a plurality of bridging elements disposed in a stagger manner between the chip bonding area and the conductive portions on the substrate, for use with multiple times of wire bonding; at least one semiconductor chip mounted on the chip bonding area, and having an active side formed with a plurality of bond pads thereon; a first set and a second set of gold wires for electrically connecting the bond pads of the semiconductor chip to the bridging elements, and the bridging elements to the bond fingers, respectively; and an encapsulant for encapsulating the semiconductor chip, the gold wires and the bridging elements.
The provision of the bridging elements is mainly to electrically interconnect the first gold wires and the second gold wires, so as to successfully perform multiple wire bonding processes. This allows electronic signals outputted from the semiconductor chip to be transmitted from the bond pads, the first gold wires, the bridging elements, the second gold wires and the bond fingers to an external circuit.
Compared with a conventional package structure experiencing only one wire bonding process, the semiconductor package of the invention carried out with multiple times of wire bonding significantly shortens a wire bonding distance in each wire bonding process, so that wire span and loop height are reduced, and wire bonding operability is improved. This therefore enhances resistance of the gold wires to mold flow impact in a molding process, so as to prevent wire sweeping or wire sagging from occurrence.